K3N3C6000D-DC cmos mask rom 4m-bit (256kx16) cmos mask rom (eprom type) general description features pin configuration K3N3C6000D-DC functional block diagram pin name pin function a 0 - a 17 address inputs q 0 - q 15 data outputs ce chip enable oe output enable v cc power(+5v) v ss ground n.c no connection n.c ce q 15 q 14 q 13 q 12 q 11 q 10 q 8 q 9 v ss q 7 q 6 q 5 q 4 q 3 q 2 q 1 a 1 a 2 a 3 a 7 a 4 a 5 a 6 dip 1 2 40 39 3 4 38 37 5 6 36 35 7 8 34 33 10 9 31 32 11 12 30 29 13 14 28 27 15 16 26 25 17 18 24 23 19 22 20 21 q 0 oe v cc a 17 a 16 a 15 a 14 a 13 a 12 a 11 v ss a 10 a 9 a 8 a 0 262,144 x 16 bit organization fast access time : 80ns(max.) supply voltage : single +5v current consumption operating : 50ma(max.) standby : 50 m a(max.) fully static operation all inputs and outputs ttl compatible three state outputs package -. K3N3C6000D-DC : 40-dip-600 the K3N3C6000D-DC is a fully static mask programmable rom organized 262,144 x 16 bit. it is fabricated using silicon gate cmos process technology. this device operates with a 5v single power supply, and all inputs and outputs are ttl compatible. because of its asynchronous operation, it requires no external clock assuring extremely easy operation. it is suitable for use in program memory of microprocessor, and data memory, character generator. the K3N3C6000D-DC is packaged in a 40-dip. a 17 x and decoder buffers a 0 y and decoder buffers memory cell sense amp. control logic matrix (262,144x16) buffers ce oe . . . . . . . . q 0 q 15 . . .
K3N3C6000D-DC cmos mask rom absolute maximum ratings note : permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to th e conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. item symbol rating unit voltage on any pin relative to v ss v in -0.3 to +7.0 v temperature under bias t bias -10 to +85 c storage temperature t stg -55 to +150 c recommended operating conditions (voltage reference to v ss , t a =0 to 70 c) item symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 0 0 0 v mode selection ce oe mode data power h x standby high-z standby l h operating high-z active l operating dout active capacitance (t a =25 c, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test conditions min max unit output capacitance c out v out =0v - 10 pf input capacitance c in v in =0v - 10 pf dc characteristics note : minimum dc voltage(v il ) is -0.3v an input pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input pins(v ih ) is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. parameter symbol test conditions min max unit operating current i cc cycle=5mhz, all outputs open ce = oe =v il , v in =0.6v to 2.4v (ac test condition) - 50 ma standby current(ttl) i sb1 ce =v ih , all outputs open - 1 ma standby current(cmos) i sb2 ce =v cc , all outputs open - 50 m a input leakage current i li v in =0 to v cc - 10 m a output leakage current i lo v out =0 to v cc - 10 m a input high voltage, all inputs v ih 2.2 v cc +0.3 v input low voltage, all inputs v il -0.3 0.8 v output high voltage level v oh i oh =-400 m a 2.4 - v output low voltage level v ol i ol =2.1ma - 0.4 v
K3N3C6000D-DC cmos mask rom test conditions item value input pulse levels 0.6v to 2.4v input rise and fall times 10ns input and output timing levels 0.8v and 2.0v output loads 1 ttl gate and c l =100pf ac characteristics (t a =0 c to +70 c, v cc =5v 10%, unless otherwise noted.) read cycle item symbol K3N3C6000D-DC08 K3N3C6000D-DC10 K3N3C6000D-DC12 unit min max min max min max read cycle time t rc 80 100 120 ns chip enable access time t ace 80 100 120 ns address access time t aa 80 100 120 ns output enable access time t oe 40 50 60 ns output or chip disable to output high-z t df 20 20 20 ns output hold from address change t oh 0 0 0 ns timing diagram read add1 add2 valid data valid data t oh t df(note) add ce oe d out t rc t ace t oe t aa note : t df is defined as the time at which the outputs achieve the open circuit condition and is not referenced to v oh or v ol level.
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